PLLSTEN0=0, PLLCLKEN0=0, PRDIV0=0
MCG Control 5 Register
PRDIV0 | PLL External Reference Divider 0 (0): Divide Factor is 1 1 (1): Divide Factor is 2 2 (2): Divide Factor is 3 3 (3): Divide Factor is 4 4 (4): Divide Factor is 5 5 (5): Divide Factor is 6 6 (6): Divide Factor is 7 7 (7): Divide Factor is 8 8 (8): Divide Factor is 9 9 (9): Divide Factor is 10 10 (10): Divide Factor is 11 11 (11): Divide Factor is 12 12 (12): Divide Factor is 13 13 (13): Divide Factor is 14 14 (14): Divide Factor is 15 15 (15): Divide Factor is 16 16 (16): Divide Factor is 17 17 (17): Divide Factor is 18 18 (18): Divide Factor is 19 19 (19): Divide Factor is 20 20 (20): Divide Factor is 21 21 (21): Divide Factor is 22 22 (22): Divide Factor is 23 23 (23): Divide Factor is 24 24 (24): Divide Factor is 25 |
PLLSTEN0 | PLL Stop Enable 0 (0): MCGPLLCLK is disabled in any of the Stop modes. 1 (1): MCGPLLCLK is enabled if system is in Normal Stop mode. |
PLLCLKEN0 | PLL Clock Enable 0 (0): MCGPLLCLK is inactive. 1 (1): MCGPLLCLK is active. |